Semiconductor Sector

We have experience in the following package design and simulation:

  • BGA crack Simulation
    To predict the failure root cause of Solder Bumps, using FEA approach in consideration of Creep strain accumulation and thermal gradient effects. To achieve this, Creep analysis is done for field operating condition; and life is calculated based on the Fatigue life equations (Darveaux method)
  • Detailed Thermal Analysis of CHIP set
    Model the chip with PCB layer details, and identify the thermal distribution, thermal resistance, etc. Parametric study of the sensible dimensions, in matter of hours
  • Random Vibration analysis on PCB with Chip set
    Identify the failure mode vibration and structural rigidity of the chip set. The different frequencies (from lab testing) are checked through FEA, and avoid the resonance of the structure, which may initiate the crack.
  • Optimization of bolt tightening torque for PCB board assembly
    Optimize the pre-bolt tightening process/screws; and identify the optimum torque; to avoid the chip failures due to the high contact pressure.